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          =             &nb= sp;            =             &nb= sp;            =             &nb= sp;            =             

&nb= sp;

VESA®        =                 Video Interface Port Standar= d

Video Electronics Standards Association

860 Hillview Court, Suite 150   =             &nb= sp;            =             &nb= sp;            =             &nb= sp;            =             &nb= sp;            =           Phone: (408) 957-9270

Milpita= s, CA 95035      = ;            &n= bsp;            = ;            &n= bsp;            = ;            &n= bsp;            = ;            &n= bsp;            = ;            &n= bsp;            = ;   FAX: (408) 957-9277

 

VESA Video Interface Port (VIP)
Version: 2<= /o:p>

 

Date:  October 21, 1998=

 

 

Purpose

 

Summary


 

VESA - The Video Electronics Standards Association

Video Interface Port (VIP) S= pecification

 

Intellec= tual Property

&nb= sp;

Copyright © 1994-1998, Video Electro= nics Standards Association.  All ri= ghts reserved.  While every precaut= ion has been taken in the preparation of this standard, the Video Electronics Standards Association and its contributors assume no responsibility for err= ors or omissions, and make no warranties, expressed or implied, of functionalit= y or suitability for any purpose.

&nb= sp;

Trademar= ks

 

All trademarks used within this document = are the property of their respective owners.&n= bsp; VESA is a registered trademark of the Video Electronics Standards Association.

&nb= sp;

Patents<= o:p>

 

VESA proposals and standards are adopted = by the Video Electronics Standards Association without regard to whether their= adoption may involve any patents or articles, materials, or processes.  Such adoption does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the proposals or standards documents.

&nb= sp;

Support<= o:p>

 

Clarifications and application notes to support this standard may be written.  To obtain the latest standard and any support documentation, contact VESA.

 

If you have a product which incorporates = VESA VIP, you should ask th= e company that manufactured your product for assistance.  If you are a manufacturer, VESA can assist you with any clarification you may require.  All comments or reported errors sh= ould be submitted in writing to VESA using one of the following methods.

 

·         Fax     &n= bsp;              &= nbsp;   408-957-9277, direct this note to Technical Suppo= rt at VESA

 

·         e-mail     = ;   support@v= esa.org

 

·         mail to    &nbs= p;  Technical Support
       &= nbsp;          VESA - Video Electronics Standards Association
       &= nbsp;          860 Hillview Court, Suite 150

Milpitas, CA 95035

 

VESA VPORT Co= mmittee Members

Any industry standard requires input from many sources.  The people listed be= low were members of the VESA VPORT Committee which were responsible for combini= ng all of the industry input into this standard:

MEMBERS

 

Chairman, Chris Lam, Innovative Semiconductors, Inc.=

Bruce Busby, 3Dfx Interactive

Max Ma, 3Dlabs, Inc.

Ed Callway, ATI Technologies, Inc.

Hiten Patel, Fujitsu Microelectronics, Inc.

Peter Sherlock, Integrated Device Technology

Nilesh Shah, Intel Corporation

Bob Matthews, LSI Logic

John Wong, Macrovision

Nick Glantzis, Matrox Technology, Inc.

Syed Zaidi, NeoMagic Corporation

Philip Wang and Morgan Tang, Oak Technology, Inc.

Leo Warmuth, Philips Semiconductors, Inc.

Ben Felts, Rockwell Semiconductors, Inc.

Steve Gibson and Kiumars Sabeti, S3, Inc.

John Gerard, Samsung Semiconductor, Inc.

Khanh Dang, SGS-THOMSON Microelectronics

Jon Kiachian and James Kim, Silicon Image, Incorpora= ted

Ken Mano, Sony Electronics, Inc.

Wen Li, Texas Instruments Semiconductors

John Matsumoto, Toshiba America Information System

Simon Hong, Trident Microsystems, Inc.

 

 

 

Table of Content

1  &nb= sp;      Overview..........................................= ...........................................................................= .................................................... 7

1.1     Scope.......................................................................= ...........................................................................= ............................. 7

1.2     What is VIP?................................................................= ...........................................................................= ...................... 7

1.3     VIP Key Features.................................................................= ...........................................................................= ......... 7

1.4     Device and Module Limitations..........................................= ........................................................................ 7

1.5     Block Diagram.................................................................= ...........................................................................= ............ 8

1.6     Signal Description.................................................................= ...........................................................................= .... 8

2  &nb= sp;      Theory of Operation........................= ...........................................................................= .......................................... 9

2.1     Note on Compatibility.................................................................= ...................................................................... 9

2.2     The Video Bus.................................................................= ...........................................................................= ................ 9

2.3     VIP Host Bus................................................................= ...........................................................................= ..................... 9

2.3.1  = ;     VIP Host Signals........................= ...........................................................................= ................................................. 9

2.3.2  = ;     Terminology..........................................= ...........................................................................= ...................................... 9

2.3.2.1 &nb= sp;        Cycle and Phase...........................= ...........................................................................= ............................................. 9

2.3.2.2 &nb= sp;        The Symbolic Signals....................= ...........................................................................= ......................................... 10

2.3.2.3 &nb= sp;        The VIP Phases..........................= ...........................................................................= ............................................ 10

2.3.3  = ;     VIP Transfer Example....................= ...........................................................................= ........................................ 11

2.3.4  = ;     Hardware Polling.............................= ...........................................................................= ......................................... 11

2.3.5  = ;     Timeout Condition...........................= ...........................................................................= ....................................... 11

2.3.6  = ;     Command/Address Bytes...............................= ...........................................................................= ....................... 12

2.3.7  = ;     Device Select Types........................= ...........................................................................= ......................................... 12

2.3.8  = ;     FIFO vs. Register Access.................= ...........................................................................= ........................................ 12

2.3.9  = ;     Burst Transfer............................= ...........................................................................= ............................................... 13

2.3.10 &nbs= p;  Predefined FIFO Ports..........................= ...........................................................................= ................................... 13

2.3.11 &nbs= p;  Status 0...................................= ...........................................................................= ................................................... 13

2.3.12 &nbs= p;  Status 1...................................= ...........................................................................= ................................................... 14

2.4     VBI Data....................................................................= ...........................................................................= ....................... 14

2.5     Power Down Mode.................................................................= ...........................................................................= .... 14

2.5.1  = ;     Power States..............................= ...........................................................................= ................................................ 14

2.5.2  = ;     Separate Power State Hazards.................= ...........................................................................= ............................. 15

2.5.3  = ;     Power Management Programming Interface....= ...........................................................................= ................. 15

2.6     Plug-and-Play.................................................................= ...........................................................................= ............. 15

2.6.1  = ;     VIP Power Up Detection..................= ...........................................................................= ....................................... 15

2.6.2  = ;     VIP Slave Devices.......................= ...........................................................................= ............................................. 15

2.6.3  = ;     Legacy 656 Devices.........................= ...........................................................................= ....................................... 15

2.6.4  = ;     Interrupt Request.............................= ...........................................................................= ........................................ 16

2.6.5  = ;     VIP Device Configuration Space..........= ...........................................................................= ................................ 16

2.6.5.1 &nb= sp;        Command Register............................= ...........................................................................= ...................................... 17

2.6.5.2 &nb= sp;        Status Register............................= ...........................................................................= ............................................ 17

3  &nb= sp;      Arbitration Scheme Analysis.....................= ...........................................................................= ....................... 18

3.1     Overview....................................................................= ...........................................................................= .................... 18

3.2     Timing Assumptions.................................................................= ...........................................................................= 18

3.3     Timing Analysis.................................................................= ...........................................................................= ........ 18

3.3.1  = ;     Round Robin Loop Timing...................= ...........................................................................= ................................. 18

3.3.2  = ;     VBI Transfer Requirements...............= ...........................................................................= .................................... 19

3.3.3  = ;     MPEG Transfer Timing.....................= ...........................................................................= ...................................... 19

3.3.4  = ;     PCI Timing..............................= ...........................................................................= .................................................. 19

4  &nb= sp;      Mechanical Specification.......................= ...........................................................................= ............................ 20

4.1     VIP Connectors.................................................................= ...........................................................................= .......... 20

4.2     I2C Bus.................................................................= ...........................................................................= ............................... 21

4.3     I2S Digital Audio Output..........................................= ...........................................................................= ............. 21

4.4     Ribbon Cable Specification..........................................= ...........................................................................= .... 21

4.5     VIP Module Mechanical Examples (PCI or A= GP)..........................................= ..................................... 21

4.6     VIP Module Side View (PCI or AGP)..........................................= .................................................................... 22

4.7     Graphics Adapter/VIP Module Attachment Example.............................= ................................... 23

4.8     VIP Module Mechanical Examples (NLX AGP)= ..........................................= .......................................... 23

4.9     VIP Module Side View (NLX AGP)..........................................= ......................................................................... <= /span>24

4.10        Component Height Considerations......................= ...........................................................................= . 24

5  &nb= sp;      Protocol Rules...............................= ...........................................................................= ............................................. 25

5.1     Retry, Wait and Data Phases..........................................= ...........................................................................= .. 25

5.2     HCTL Tri-state Rules.................................................................= ........................................................................ 26

5.3     HAD Tri-state Rules.................................................................= .......................................................................... = 26

5.4     The Idle Phase.................................................................= ...........................................................................= ............ 26

5.5     The Command Phase.................................................................= .......................................................................... = 27

5.6     The Address Phase.................................................................= ...........................................................................= ... 27

5.7     The Decode Phase.................................................................= ...........................................................................= ..... 27

6  &nb= sp;      Timing Diagrams............................= ...........................................................................= ............................................... 28

6.1     Figure 1:  Register read, 1 byte, no wait sta= tes, master terminated...................= ......... 28

6.1.1  = ;     Command Phase...............................= ...........................................................................= ...................................... 28

6.1.2  = ;     Address Phase...............................= ...........................................................................= ............................................ 28

6.1.3  = ;     Decode Phase...............................= ...........................................................................= ............................................ 28

6.1.4  = ;     Retry Phase...............................= ...........................................................................= ................................................ 28

6.1.5  = ;     Data Phase...............................= ...........................................................................= ................................................. 29

6.1.6  = ;     Turn-Around Phase...............................= ...........................................................................= .................................. 29

6.2     Figure 2:  FIFO burst write, master terminate= d..........................................= .................................. 29

6.3     Figure 3:  FIFO write, retry (slave terminate= d)..........................................= ................................... 31

6.4     Figure 4:  FIFO read, retry (slave terminated= )..........................................= ..................................... 31

6.5     Figures 5 and 6:  Register Accesses with wait states, master and slave termination  &nb= sp;      33

6.6     Figures 7 and 8:  FIFO burst transfers, master and s= lave termination....................... <= /span>35

6.7     Figures 9 and 10.  Timeout Cycles.................................................................= ............................................ 35

6.8     VIP Video Port.................................................................= ...........................................................................= ............. 38

6.8.1  = ;     YUV (YCbCr) Byte Ordering...............= ...........................................................................= .................................. 38

7  &nb= sp;      Electrical Specification.......................= ...........................................................................= .............................. 39

7.1     VIPCLK - DC Requirements..........................................= ...........................................................................= ......... 39

7.2     All signals except VIPCLK - DC Requireme= nts..........................................= ....................................... 39

7.3     AC Requirements.................................................................= ...........................................................................= ...... 40

8  &nb= sp;      VIP Video Format........................= ...........................................................................= .................................................. 41

8.1     Overview....................................................................= ...........................................................................= .................... 41

8.2     SAV and EAV codes for active video..........................................= ............................................................. 43

8.3     Ancillary data blocks with ANC header..........................................= ............................................... 44

8.4     Sliced VBI data.................................................................= ...........................................................................= .......... 44

8.5     Digital Audio PCM.................................................................= ...........................................................................= .... 46

9  &nb= sp;      VIP2 Extensions..........................= ...........................................................................= .................................................... 48

9.1     Overview....................................................................= ...........................................................................= .................... 48

9.2     VIP2 Signal Description..........................................= ...........................................................................= .............. 49

9.3     The Host Port.................................................................= ...........................................................................= ............. 49

9.3.1  = ;     HOST_CAP[1:0]..........................................= ...........................................................................= ............................ 49

9.3.2  = ;     XHOST_ON..........................................= ...........................................................................= .................................... 50

9.3.3  = ;     MY_IRQ..........................................= ...........................................................................= .......................................... 50

9.3.4  = ;     VIP2 Registers...........................= ...........................................................................= ............................................... 50

9.3.4.1 &nb= sp;        The Command Register (009:008)..........= ...........................................................................= ................................ 50

9.3.4.2 &nb= sp;        The Status Register (00B:00A)...........= ...........................................................................= .................................... 50

9.3.4.3 &nb= sp;        Reserved Registers...........................= ...........................................................................= ....................................... 50

9.3.4.4 &nb= sp;        Status 0 (FIFO Port 0).....................= ...........................................................................= ....................................... 51

9.3.5  = ;     Extended Data Transfer.......................= ...........................................................................= .................................. 51

9.3.5.1 &nb= sp;        Standard Mode................................= ...........................................................................= ........................................ 51

9.3.5.2 &nb= sp;        4-bit Mode................................= ...........................................................................= .............................................. 51

9.3.5.3 &nb= sp;        8-bit Mode................................= ...........................................................................= .............................................. 51

9.3.6  = ;     The SIZE[1:0] Bits......................= ...........................................................................= ............................................. 53

9.4     The Video Port.................................................................= ...........................................................................= ........... 53

9.4.1  = ;     Extended Video Mode..........................= ...........................................................................= .................................. 53

9.4.2  = ;     Video Flags...............................= ...........................................................................= ................................................. 54

9.4.3  = ;     New Video Flags.........................= ...........................................................................= .............................................. 54

9.4.4  = ;     Extra Flag Bytes..........................= ...........................................................................= ............................................. 54

9.4.5  = ;     The Task Bit............................= ...........................................................................= ................................................. 55

9.5     VIP2 Level System.................................................................= ...........................................................................= .... 55

9.5.1  = ;     Level III Dual Stream Mode................= ...........................................................................= ................................. 55

9.5.2  = ;     XVID Video Encoder Support...............= ...........................................................................= ................................ 56

9.6     The Extended Pin Assignment..........................................= ...........................................................................= 56

9.7     VIP2 Module Mechanical Example..........................................= ................................................................ 57

10  &n= bsp;   Appendix A: DTV Formats......................= ...........................................................................= .................................. 58

10.1        References..........................................= ...........................................................................= ..................................... 58

10.2        DTV Resolutions..........................................= ...........................................................................= ......................... 58

10.3        8-bit VIP Video Stream Formats.............................= ...........................................................................= .... 59

10.3.1 &nbs= p;  Horizontal Blanking Interval and Ancillary Data Formats...................................................................= ..... 59

10.4        DTV Display Formats..........................................= ...........................................................................= ............... 61

10.4.1 &nbs= p;  Summary of EAV Transitions for Video Format Protocols..................................................................= ...... 61

10.4.2 &nbs= p;  Protocol for 525-line(NTSC) Interlace Video..= ...........................................................................= ................... 61

10.4.3 &nbs= p;  Protocol for 625-line(PAL) Interlace Video...= ...........................................................................= ..................... 63

10.4.4 &nbs= p;  Protocol for 704x480 Progressive Video.......= ...........................................................................= ...................... 65

10.4.5 &nbs= p;  Protocol for 1280x720 Interlace Video........= ...........................................................................= ....................... 66

10.4.6 &nbs= p;  Protocol for 1280x720 Progressive Video......= ...........................................................................= ..................... 68

10.4.7 &nbs= p;  Protocol for 1920x1080 Interlaced Video......= ...........................................................................= .................... 70

10.4.8 &nbs= p;  Protocol for Data Packet Mode................= ...........................................................................= ............................ 72

10.4.8.1 &n= bsp;            8-bit Data Packet Format..................= ...........................................................................= ................................. 72

10.4.8.2 &n= bsp;            16-bit Data Packet Format..................= ...........................................................................= ............................... 72

 

 

This specification describes the VESA VIP2 Standard.  VIP2 is backward compatible with VIP1.1.  The first eight chapt= ers of this document cover VIP1.1, while chapter 9 and beyond cover the VIP2 extensions. =

Vi= deo Interface Port, VIP, is a standard interface between a “video-enabled” graphics chip and one or more video devices (e.g. MPEG2 decoder, video decoder).  The key objectives for VIP are:

·         Common open standard for all new graphics ch= ips and PC-oriented video devices

·         Low cost

·         Low Pin Count

·         Support multiple devices concurrently

·         Adequate performance for today and future applications

·         Requires only 14-signal pins from the graphi= cs chip for a typical implementation

·         Separate video and host control ports

·         26-pin VIP Connector port; can coexist with = VESA Feature Connector

·         Separate 14-pin connector for power, reset, = and I2S digital audio

·         Supports one video module and one ribbon cab= le board simultaneously

·         Supports up to four VIP slave devices

·         Plug-and-play support through the graphics c= hip PCI interface

·         Video Port

= ·         Simplified ITU-R-656 Video Format -- supports HSYNC, VSYNC, ODD FIELD, EVEN FIELD, and ANCILLARY DATA functions

= ·         VBI data output from video decoder is through ITU-R-656 Ancillary Data or through the host port

= ·         Supports variable video resolutions and scan rates

= ·         Supports both interlaced and non-interlaced video

·         Host Port

= ·         Synchronous bus with clock frequency ranging from 25MHz to 33MHz

= ·         Two data bits; it takes 4 cycles to transfer= one byte

= ·         Supports burst mode, master or slave-termina= ted transfers, wait-states, and timeout transfers

 

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   &nbs= p;            &= nbsp;           &nbs= p;            &= nbsp;           &nbs= p;            &= nbsp;           &nbs= p;            &= nbsp;   

VESA Video Interface Port (VIP)        &= nbsp;           &nbs= p;            &= nbsp;           &nbs= p;            &= nbsp;           &nbs= p;            &= nbsp;           &nbs= p;            &= nbsp;           &nbs= p;             = Page 7 of 72

ÓCopyright 1994-1998 Video Electronics Standards Association            =             &nb= sp;            =             &nb= sp;            =             &nb= sp;       Version 2

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