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&nb= sp;

        =             &nb= sp;           Flat Panel Display Interface -2 Standard

=

Video Electronics Standards Association

860 Hillview Court, Suite 150   =             &nb= sp;            =             &nb= sp;              =                   Phone: (408) 957-9270

Milpita= s, CA 95035        &= nbsp;           &nbs= p;            &= nbsp;           &nbs= p;            &= nbsp;           &nbs= p;            &= nbsp;         Fax: (408) 957-9277

 

Flat Panel Display Interface -2
 

Version: 1

February 14, 1998

&nb= sp;

Purpose<= /span>

 

The purpose of this standard is to define= an electrical, logical, and connector interface for flat panel displays.  The usage is within closed environ= ments, typically notebook computers or monitor enclosures. 

 

Summary<= /span> 

 

Earlier standards, FPDI-1 and FPDI-1B, we= re compilations of existing flat panel display specifications in production at that time.  FPDI-2 defines a c= ommon interface that is display technology independent and scalable through HDTV addressabilities.  The goal is= to reduce flat panel display manufacturers design costs, system integration co= sts, and time to market.

 

 

Intellectual Property

 

Copyright= 1997 - Video Electronics Standards Association.=   All rights reserved.

 

While every precaution has been taken in the preparati= on of this standard, the Video Electronics Standards Association and its contribu= tors assume no responsibility for errors or omissions, and make no warranties, e= xpressed or implied, of functionality or suitability for any purpose.

 

Trademarks<= /span>

 

All trademarks used within this document are the property of their respective owners.  VESA is a registered trademark of the Video Electronics Standards Association.

 

VESA, DDC, EVC, EDID, P&D and FPDI are trademarks of = the Video Electronics Standards Association.

PanelLinkTM , TMDS are trademarks of Silicon Image, Inc.

I2C is a trademark of Philips Semiconductor.

 

Patents

 <= /b>

VESA proposals and standards are adopted by the Video Electronics Standards Association without regard to whether their adoption may involve any patent= s or articles, materials, or processes.  Such adoption does not assume any liability to any patent owner, nor= does it assume any obligation whatever to parties adopting the proposals or standards  documents.

 

Support

 

Clarifications and application notes to support this standard may be written.  To o= btain the latest standard and any support documentation, contact VESA.

 

If you have a product which incorporates Flat Panel Di= splay Interface-2, you should ask the company that manufactured your product for assistance.  If you are a manufacturer, VESA can assist you with any clarification you may require.  All comments or reported errors sh= ould be submitted in writing to VESA using one of the following methods.

 

·         Fax &nb= sp;            =    408-957-9277, direct this note to Technical Suppo= rt at VESA

 

·         e-mail =             s= upport@vesa.org

 

·         mail to = ;          Technical Support

   &nbs= p;            &= nbsp;           &nbs= p;   VESA

   &nbs= p;            &= nbsp;           &nbs= p;   860 Hillview Court, #150

   &nbs= p;            &= nbsp;           &nbs= p;   Milpitas, CA 95035

 

FPDI-2 Workgroup Members

 

Effective industry standard requires input from many sources.  The FPDI Committee m= embers listed below were instrumental in providing valuable industry input into th= is proposal.

 

Larry Kopp, AMP Incorporated

Earl Myers, AMP Incorporated

Bill Russell, Canon Information Systems

Lee Farrell, Canon Information Systems

Ben Burge, Chips & Technologies, Inc.

Kirk Lowry, Chips & Technologies

Bob Myers, Hewlett-Packard

Karl Kwiat, Hirose Electric (USA) Inc.

Mike Marentic, Hitachi America, Ltd.

Wayne Uenishi, Hosiden Corporation

Ian Miller, IBM Corporation

Shaun Kerigan, IBM Corporation

Don Chambers, JAE Electronics, Inc.

Edgardo Rodriguez-Crespo, Mitsubishi Electronics Ameri= ca, Inc.

Dave Rios, Molex Incorporated

Gary Manchester, Molex Incorporated

Kingo Takahashi, NEC Electronics, Inc.

Jack Hosek, NEC Technologies, Inc.

Chet Bassetti, NeoMagic Corporation

John Roberts, NIST

Hans Van der Ven, Panasonic

Mike Phillips, Panasonic

Heon Su Kim, Samsung Electronics Co., LTD

Mark Waring, Sharp Electronics Corporation

Scott Slinker, Silicon Image

Jon Kiachian, Silicon Image

Joe Miseli, Sun Microsystems, Inc.

Mike Blashe, Toshiba America Electronic Components=

Osamu Tomita, Toshiba America Electronic Components=

David O’Dell, VLSI Technology

Chris Tut= t, Vermont Electromagnetics, C= orp.

Alain D’Hautecourt, Viewsonic

 

 

 

 

Table of Contents=

1. Introduction.....................................................................= ...........................................................................= ......................

1.1 Overview............................= ...........................................................................= ....................................................................

1.2 References..........................= ...........................................................................= .................................................................

2. Connector Interface = Pin Assignment..........................= ...........................................................................= .....

2.1 Pin Assignments for the Mandatory 20-Contact Position Connector Interface.....

2.2 Pin Assignments For The Optional 8-Contact Position Connector Interface..............

3. Electrical Layer Specification.......................= ...........................................................................= ....................

3.1 Transition Minimized Differential Signaling Interface...........................................................

3.1.1 Overview..........................................= ...........................................................................= .................................................

3.1.2 Logical Architect= ure..........................................= ...........................................................................= .............................

3.1.3 Summary..........................................= ...........................................................................= ..................................................

3.1.4 TMDS Transmitter<= span style=3D'mso-tab-count:1 dotted'>..........................................= ...........................................................................= .................................

3.1.5 TMDS Receiver Sum= mary..........................................= ...........................................................................= .....................

3.1.6 Relationship Betw= een Controller’s Output Data and Input Data Clock........................................................ <= /span>

3.2 Transition-Controlled Digital Encoding and Signal Transmission.................................. =

4. Digital Data Formats= ..........................................= ...........................................................................= ...........................

4.1 Summary Table.......................= ...........................................................................= ........................................................

4.2 Per Transfer Detail Tables..........= ...........................................................................= .........................................

5. Initialization Contr= ol Communication.......................= ...........................................................................= ..

6. Power Sequencing..........................................= ...........................................................................= ...................................

6.1 Introduction........................= ...........................................................................= ............................................................ =

6.2 Notebook Case.......................= ...........................................................................= .......................................................... GOTOBUTTON _Toc403805724  34

6.3 Monitor Case........................= ...........................................................................= ............................................................ =

7. Connector Interface<= span style=3D'mso-tab-count:1 dotted'>..........................................= ...........................................................................= ...........................

7.1 Introduction........................= ...........................................................................= ............................................................ =

7.2 Receptacle Connector................= ...........................................................................= .............................................

7.3 Plug Connector......................= ...........................................................................= ........................................................

7.3.1 Alternate Transmi= ssion Media Termination...................= ...........................................................................= ...........

7.3.2 Recommended Flexi= ble Etched Circuit Interconnection (Alternative to Plug).............................................

7.4 Recommended Contact Platings........= ...........................................................................= ...............................

7.5 Connector Performance Characteristics..........................................................................= .................

7.5.1 Electrical..........................................= ...........................................................................= ................................................

7.5.2 Mechanical..........................................= ...........................................................................= .............................................

7.5.3 Environmental..........................................= ...........................................................................= .......................................

8. Compliance, Troubles= hooting, Verification........................= ................................................................

8.1 System De-Bug on Differential Data Pairs.......................................................................= ......................

8.2 Signal Bandwidth Characteristics....= ...........................................................................= ............................

8.3 Electrical Characteristics..........= ...........................................................................= ......................................

8.4 DC Electrical Specifications...........= ...........................................................................= ....................................

8.5 Driver Output Levels................= ...........................................................................= .................................................

8.6 Signal Integrity....................= ...........................................................................= ........................................................

8.6.1 Jitter and Skew o= f Clock and Differential Data Pairs.........= ...........................................................................= ....

8.6.2 Eye Diagram Templ= ate..........................................= ...........................................................................= .........................

8.7 AC Specifications......................= ...........................................................................= .....................................................

8.7.1 Timing Diagrams..........................................= ...........................................................................= ...................................

8.8 Error Specification for TMDS Interface GOTOBUTTON _Toc403805748  59

8.9 Guidance for Display Controller Implementation.................................................................= ......

 

List of Figures

Figure 3-1:  Simplified Block Diagram of an  Interface with Clock and RGB.......................... <= !--[if supportFields]> GOTOBUTTON _Toc403805750  12

Figure 3-2:  Transition Minimized  Differential Voltage Swing Adjust<= span style=3D'mso-tab-count:1 dotted'>........................................ <= /span>

Figure 3-3:  Single Ended Transition Minimized Differential Signal Adjustment................

Figure 3-4:  System Environment Block Diagram Example.....................= ...............................................

Figure 3-5:  Video Transmitter IC Functional Block Diagram............= ................................................

Figure 3-6:  Typical CMOS Circuits fo= r TMDS Driver..............................= ......................................................

Figure 3-7:  Video Receiver IC Functi= onal Block Diagram.......................= ..............................................

Figure 3-8:  Horizontal Input Timing = at Type B Interface....................= ..................................................

Figure 3-9:  Vertical Input Timing at= Type B Interface.........................= ....................................................

Figure 3-10:  Input Data Timing with Respect to IDCK at Type B Interface.= ................................

Figure 3-11:  Control Signal Timing w= ith Respect to IDCK at Type B Interface.= .....................

Figure 3-12:  Control Signals with Re= spect to DE Timing........................= ................................................

Figure 3-13:  TMDS Interface Transiti= on Minimization Timing Diagram.........= .............................

Figure 3-14:  Encoded Timing Diagram = for All Differential Data Pair..........= ...............................

Figure 3-15:  HSYNC, VSYNC, and CTL[3= :1] Sampling Relative to Clock Edge.....= .............................

Figure 6-1:   Block Diagram of Notebook Case.......................= ......................................................................... <= /span>

Figure 6-2: Power-up Sequencing for the Notebook Case.................................................................= .......

Figure 6-3: Power-down Sequencing for the Notebook Case................................................................ =

Figure 6-4:   Block Diagram of M= onitor Case................................= ................................................................... =

Figure 6-5:   Power-Up and Hot-Plugging Flowchart for P&D-D (TMDS) Monitor......................

Figure 7-1: Receptacle Connector Mating Interface Defining Features...................................

Figure 7-2 Recommended PCB Layout For The Receptacle Connector..........................................

Figure 7-3: Recommended Plug Connector Mating Interface Features......................................

Figure 7-4: Recommended FEC Mating Interface Features.................................................................= ...

Figure 8-1:  Differential Mode Impeda= nce..........................................= ................................................................

Figure 8-2: Signal Levels on Transmission Media.......................................................................= ..................

Figure 8-3:  Driver and Receiver Circ= uit Model for One Differential Data Pair= ..................

Figure 8-4:  Direct Coupling for Note= book Case................................= ............................................................ =

Figure 8-5:  Capacitor - Coupled for Monitor Case........................= ..............................................................

Figure 8-6:  Timing Diagram for Jitte= r and Skew Specification..................= .......................................

Figure 8-7:  TMDS Connection..........................................= ...........................................................................= ..................

Figure 8-8:  Eye Diagram Mask at Poin= t S..........................................= ................................................................... =

Figure 8-9:  Eye Diagram Mask at Poin= t R..........................................= .................................................................. <= /span>

Figure 8-10.  Transmitter Small Signal Transition Times....................= ..................................................

Figure 8-11.  Receiver Digital Output Transition Times....................= .......................................................

Figure 8-12.  Transmitter/Receiver Cl= ock Cycle/High/Low Times................= ...................................

Figure 8-13.  Differential Data Pair-= to-Differential Data Pair Skew Timing...............= ............

Figure 8-14.  Input Data Setup/Hold T= imes to IDCK of Transmitter..............= .....................................

Figure 8-15.  DE, VSYNC, HSYNC, and CTL[3:1] Setup/Hold Times to IDCK of Transmitter........

Figure 8-16.  VSYNC, HSYNC, and CTL[3= :1] Delay  Times from DE of Transm= itter.......................... <= !--[if supportFields]> GOTOBUTTON _Toc403805789  57

Figure 8-17.  DE High/Low Times of Transmitter.........................= ....................................................................

Figure 8-18.  PLL_SYNC Timing of Transmitter with SYNC_CONT =3D 1....= ................................................

Figure 8-19.  PLL_SYNC Timing of Transmitter with SYNC_CONT =3D 0....= ................................................

Figure 8-20.  Output Signals Disabled/Enabled Timing from PD Active/Inactive from Transmitter        &= nbsp;  

Figure 8-21.  Differential Clock Dela= y from IDCK................................= .......................................................

Figure 8-22:  Line Error Rate..........................................= ...........................................................................= ...................

Figure 8-23:  Full Frame Error Rate..........................................= ...........................................................................= ..

 

List of Tables

Table 2= -1: Pin Assignments for Mandatory 20-Contact Position Connector Interface...

Table 2-2: Pin Assignments for Optional 8-Contact Position Connector Interface...........

Table 3-1: Theoretical Low-Voltage, Single-Ended Differential Swing Level Relativ= e to REXT_SWING   &nbs= p;      

Table 3-2:  Addressability Table..........................................= ...........................................................................= .........

Table 3-3:  Encoder Mapping for a Si= ngle Differential Data Pair..............= ......................................

Table 3-4:  Signal Name Description<= span style=3D'mso-tab-count:1 dotted'>..........................................= ...........................................................................= ..

Table 3-5:  Encoded Data Components = for TMDS Data 0 Differential Data Pair..= ...................

Table 3-6:  Encoded Data Components = for TMDS Data 1 Differential Data Pair..= ...................

Table 3-7:  Encoded Data Components = for TMDS Data 2 Differential Data Pair..= ...................

Table 4-1:  Data Format Summary..........................................= ...........................................................................= .......

Table 4-2:  Data Format for Monochro= me, Dual-Scan STN with 8 bits each to Upper and Lower Sub-panel..........................................= ...........................................................................= ...........................................................................= .

Table 4-3:  Data Format for Color, Single-Scan STN with 16 bits........= ..............................................

Table 4-4:  Data Format for Color, Dual-Scan STN with 8 bits each to Upper and Lower Sub-panel        &= nbsp;   

Table 4-5:  Data Format for Color, Dual-Scan S= TN with 12 bits each to Upper and Lower Sub-panel          

Table 4-6:  Data Format for Color, T= FT with 6 bits Per Primary Color.......= .................................

Table 4-7:  Data Format for Color, T= FT with eight bits per Primary Color...= ..........................

Table 8-1:  System Debug Patterns..........................................= ...........................................................................= ......

Table 8-2:  Distributed Transmission= Path Bandwidth and Rise-Time.............= ..............................

Table 8-3:  Receiver  Specifications for TMDS Input..........................................= ..........................................

Table 8-4:  Component Values for Fig= ure 8-5.................................= ....................................................................

Table 8-5:  Signal Integrity Paramet= ers..........................................= .................................................................. <= /span>

Table 8-6:  Eye Diagram Mask at Poin= t S*..........................................= .................................................................. <= /span>

Table 8-7:  Eye Diagram Mask at Poin= t R*..........................................= .................................................................. <= /span>

Table 8-8: AC Specifications..............= ...........................................................................= ................................................

 

Terms and Abbreviation= s

 

Term or Abbreviation=

Description

ASIC

Application Specific Integrated Circuit

CRT

Cathode Ray Tube

CMOS

Complimentary Metal Oxide Semiconductor

DDC

VESA Display Data Channel

DDC2B

Simplest of the VESADDC2 modes defined in VESA DDC standard

DDC2B+

Adds bi-directional communications to VESA DDC2B

DDC2AB

An ACCESS.bus mode defined in VESA DDC standard

DPMS

VESA Display Power Management Signaling

DSTN

Dual Scan Super Twist Nematic LCD

EDID

VESA Extended Display Identification Data

EMI

Electromagnetic Interference

EVC

VESA Enhanced Video Connector

FEC

Flexible Etched Circuit

FPD

Flat Panel Display

FPDI

VESA Flat Panel Display Interface

HDTV

High Definition Television

IEEE 1394

High Performance Serial Bus Standard

IC

Integrated Circuit

I2C

Trademark of Philips, Inter IC or I2C - B= us

LCD

Liquid Crystal Display

LVDS

Low Voltage Differential Signaling1

Logical Layer

Indicates a section of code

MCCS

VESA Monitor Control Command Set

P&D

VESA Plug and Display standard

PanelLinkä

Trademark of Silicon Image

PCB

Printed Circuit Board

PLL

Phase Lock Loop

Physical Layer

Indicates a physical layer, electrical or mechanical=

RGB2S

Red, Green & Blue Video, HSYNC and VSYNC

Rxn

TMDS Receiver Number ‘n’

TFT

Thin Film Transistor LCD

TMDS

Transition Minimized Differential Signaling2

TTL

Transistor, Transistor Logic

Txn

TMDS Transmitter number ‘n’

USB

Universal Serial Bus

VESA

Video Electronics Standards Association

 

1  The term LVDS is used in this docu= ment as a generic term and does not imply any particular LVDS technology.

2  The term TMDS, a trademark of Sili= con Image, Inc., will generally be used in this document to denote PanelLinkä or compatible technologies.

1.&n= bsp;    Introduction

1.1&= nbsp;     Overview

This standard describes the electrical, logical, and c= onnector interface for a flat panel display.  The FPD with its standardized interface will be used in mobile computers, desktop monitors, or in embedded industrial applications.  The electrical signal layer is Pan= elLinkTM  Technology developed = by Silicon Image, Inc. of Cuperti= no, California (www.SiImage.com= ), hereafter called Transition Minimized Differential Signaling (TMDS).  The TMDS technology converts paral= lel data to high speed serial data.  The serial data is transmitted over suitable transmission media to the defined interface connector of this standard.  The TMDS receiver mounted on the FPD reconverts the serial data to parallel data usable by the FPD.  This standard defines a connector interface and pin assignment but d= oes not define a suitable transmission media construction.  The pixel data format transmitted = over the suitable transmission media is defined in this standard.  Initialization control using VESA = DDC2B for transmission of  VESA EDID, Version 3.0, data block is optional.  The LCD backlight connector interface, inverter, and luminance contr= ol is outside the scope of this document.

The envisioned usage for a compliant FPD is in closed systems, typically notebook computers or desktop monitors.  The connector is rated as an inter= nal connector.  The electrical and logical interface can extend outside the closed environment.  An optional monitor bulkhead conne= ctor interface is described in the VESA P&D standard.

The VESA P&D standard defines the video port for t= he host system using TMDS.  The F= PDI-2 standard is fully compatible with and is an extension of that standard as t= he receiver of the video data.  T= he dual use FPDI-2 display provides for the following:

·         Compatibility with video graphics controllers using integrated TMDS transmitters,

·         Reduction of the number of software device drivers that need to be written,

·         Reduction of the system integrator’s display inventory,

·         Independence of the display technology ,

·         Enables FPD manufacturers to produce a common panel interface regardless of size and resolution requirements.

1.2&= nbsp;     References=

Sev= eral standards are referenced by this document and should be considered a part of the FPDI-2 specification.

 

Name of Standard

Version /

 Reference #

Date of Issue

ANSI/EIA-364—1994, Electrical Connector /Socke= t Test Procedures Including Environmental Classifications

C

Nov. ‘94

ACCESS.bus Specification

3.0

Sept.  ‘95

ASME Y14.5M-1994

 <= /span>

Jan.   ‘95

IEC 801-1, Electromagnetic compatibility for industr= ial-process measurement and control equipment. Part 1 - General introduction

1984-11

 

VESA Display Data Channel (DDC)

3.0

Dec. ‘97

VESA Display Power Management Signaling (DPMS)

1.0

Aug. ‘93

VESA Extended Display Identification Data (EDID)

3.0

Nov. ‘97

VESA Flat Panel Display Interface Timing

 

 

VESA Monitor Control Command Set (MCCS)

0.9p

June ‘97

VESA Plug and Display (P&D)

1.0

June ‘97

 

 

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