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DPVL Standard

VESA        &= nbsp;           &nbs= p;        

Video Electronics Stan= dards Association

860 Hillview Court, Su= ite 150        &= nbsp;           &nbs= p;            &= nbsp;           &nbs= p;            &= nbsp;       Phone: (408) 957-9270

Mil= pitas, CA 95035        &= nbsp;           &nbs= p;            &= nbsp;           &nbs= p;            &= nbsp;           &nbs= p;            &= nbsp;           &nbs= p;            &= nbsp; Fax:     (408) 957-9277

 

VESA DIGITAL PACKET VIDEO LINK STANDARD

 

Version 1

 

April 18, 2004

Purpose

The purpose of th= is standard is to define Digital Packet Video Link (DPVL), a high-level video stream protocol, which facilitates the advancement of high information cont= ent monitors independently of whether displaying that high information content = is achieved within a single monitor unit or by an array of monitors. This stan= dard defines video packet structures, a capability management scheme and a monit= or control scheme.

 

Summary

Due to recent adv= ances in display manufacturing technologies, display devices are now able to prov= ide much higher information content – both at higher pixel-density and at= higher numbers of pixels. One of the issues that limit the wide adoption of high information content monitors is the monitor interface, since these monitors require much higher transmission bandwidth than conventional monitor interf= aces can provide. DPVL solves this problem by providing selective refresh while still utilizing conventional digital monitor interfaces. The selective refr= esh allows the host to transmit only modified regions of the screen. Thus, the video transmission rate is decoupled from the refresh rate of the display device and much lower transmission rates can ensue. This protocol can also = be used in bandwidth and/or power constrained systems. On the host side, it is= the intention of this DPVL protocol to avoid the requirement of building specia= lized graphics hardware. Rather, the changes are limited to an additional software layer which resides above the video device driver and generates DPVL video packets with the aid of the driver instead of full raster scans of the video memory contents.

Preface<= /span>

 

Intellectual Property<= /span>

Copyright © 2004= Video Electronics Standards Association.  All rights reserved.

 

While every precautio= n has been taken in the preparation of this standard, the Video Electronics Stand= ards Association and its contributors assume no responsibility for errors or omissions, and make no warranties, expressed or implied, of functionality or suitability for any purpose.

 

Trademarks<= span style=3D'font-size:14.0pt;mso-bidi-font-size:10.0pt'>

All trademarks used w= ithin this document are the property of their respective owners. VESA, DDC and EDID are trademarks of the Video Electronics Standard Association. I2C is= a trademark owned by Philips. [Other trademarks may be listed here.]

 

Patents

VESA proposals and st= andards are adopted by the Video Electronics Standards Association without regard a= s to whether their adoption may involve any patents or articles, materials, or processes. Such adoption does not assume any liability to any patent owner,= nor does it assume any obligation whatsoever to parties adopting the proposals = or standards documents.

 

Support for this Stand= ard

Clarifications and application notes to support this standard may be written. To obtain the la= test standard and any support documentation, contact VESA.

 

If you have a product= , which incorporates a DPVL, you should ask the company th= at manufactured your product for assistance. If you are a manufacturer, VESA c= an assist you with any clarification you may require. All comments or reported errors should be faxed to VESA:

 

·      =    FAX:        &= nbsp; 408-957 9277, direct this fax to Technical Support at VESA

·      =    email:         = support@vesa.org

·      =    Mail:        &= nbsp; VESA

860 Hillview Court, Ste. 150

Milpitas, CA 95035

 

  &nbs= p;        

 

 

 

 

 

 

 

 

 

 

 

Acknowledgments=

 

This document would not have been possible without the efforts of the VESA DPVL Committee. In particular, the following individ= uals and their companies contributed significant time and knowledge to this document.

 

David Glen

ATI Technologies, Inc.

 <= /o:p>

Jack Hosek

NEC-Mitsubishi

Zhiling Lai

ATI Technologies, Inc.

 <= /o:p>

Jeff Irwin

NVIDIA

Takashi Matsui

EIZO NANAO

 

George Wiley

Qualcomm

Jim Webb

Genesis Microchip

 

Ian Miller

Samsung Electronics

Steve Millman

IBM

 <= /o:p>

Perry Robertson

Sandia National Labs

Kai Schleupen

IBM

 <= /o:p>

L= yndon G. Pierson

S= andia National Labs

Moriyoshi Ohara

IBM Japan

 

J= oe Lamm

T= ech SourceSteve McGowan

Intel

 

Timothy Miller

Tech Source

David Tran

Intel

 <= /o:p>

Alain d’Hautecourt

ViewSonic

Eric Wogsberg

Jupiter Systems

 <= /o:p>

 

 

 

 

 <= /o:p>

 

 

<= o:p> 

<= o:p> 

Revi= sion History

<= o:p> 

<= st1:date Year=3D"2004" Day=3D"18" Month=3D"4" w:st=3D"on">April 18, 2004    Initial release of the standard
T= able of Contents

1.    Preface..= ...........................................................................= ...........................................................................= ....................... 7

1.1   &= nbsp;  Definitions and Conventions..........................................= ...........................................................................= ...... 7

1.2   &= nbsp;  Glossary.................................................................= ...........................................................................= ............................. 7

2.    Overview.= ...........................................................................= ...........................................................................= .................... 9

2.1   &= nbsp;  Summary.................................................................= ...........................................................................= ............................. 9

2.2   &= nbsp;  Background.................................................................= ...........................................................................= ..................... 9

2.3   &= nbsp;  Objectives of DPVL..........................................= ...........................................................................= .............................. 9

2.4   &= nbsp;  Reference Documents<= span style=3D'mso-tab-count:1 dotted'>..........................................= ...........................................................................= ...................... 9

3.    DPVL – Principles = of Operations.................................................................= .................................................. 11

3.1   &= nbsp;  Architecture.................................................................= ...........................................................................= ............... 11

3.2   &= nbsp;  DPVL Frame Structure..........................................= ...........................................................................= ................... 12

3.3   &= nbsp;  Video Mode Control..........................................= ...........................................................................= ........................ 12

3.3.1       Special Vertical Blanking Timing Which Indicates DPVL Mode..........................................= ........................ 13

3.3.2&= nbsp;      Other Events.........= ...........................................................................= ......................................................................... <= /span>14

3.4   &= nbsp;  Video Timings..........................................= ...........................................................................= ....................................... 16

3.5   &= nbsp;  Error Control..........................................= ...........................................................................= .................................... 16

3.5.1       Monitor Requirements.........= ...........................................................................= ....................................................... 17

3.5.2       Host Requirements= .........= ...........................................................................= .............................................................. 17

3.6   &= nbsp;  Side Channel for Monitor Control and Capability Management..................................... 18

3.6.1&= nbsp;      Display Data Channel (DD= C).........= ...........................................................................= ........................................... 18

3.6.2&= nbsp;      Hot Plug Detect (HPD) fo= r DPVL host...................................................................= ............................................. 18

3.6.3&= nbsp;      Universal Serial Bus (US= B).........= ...........................................................................= ............................................... 19

3.7   &= nbsp;  Multi-Monitor Support..........................................= ...........................................................................= ................. 19

3.8   &= nbsp;  Power Management= ..........................................= ...........................................................................= ......................... 21

3.8.1&= nbsp;      DVI Link Shutdown under DPVL...............................= ...........................................................................= ............... 21

3.8.2&= nbsp;      Disabling the DVI Link u= nder DPVL...................................................................= ................................................ 22

3.8.3&= nbsp;      DVI Operation during Link Shutdown under DPVL..........................................= .............................................. 22

3.8.4&= nbsp;      Reactivation of the DVI = Link under DPVL.................................................................= ........................................ 22

3.8.5&= nbsp;      Link Shutdown Compliance= under DPVL...................................................................= ....................................... 23

3.9   &= nbsp;  Scene Syncing Feature..........................................= ...........................................................................= .................. 23

3.10    = Genlock Feature..........................................= ...........................................................................= ............................... 26

3.11    = Throttling Mechanism..........................................= ...........................................................................= ................ 26

4.    Packet Definitions..................................................................= ...........................................................................= ..... 29

4.1   &= nbsp;  Header Format and Packe= t..........................................= ...........................................................................= ....... 29

4.2   &= nbsp;  Basic Packet..........................................= ...........................................................................= ......................................... 30

4.3   &= nbsp;  Extended Packets..........................................= ...........................................................................= ............................. 32

4.3.1       Video Packet (required capability for extended m= ode)..........................................= ......................................... 40

4.3.2       Genlock Packet......................................................................= ...........................................................................= ....... 41

4.3.3       Scaled Video Streams................................................................= ...........................................................................= .. 42

4.3.4&= nbsp;      Gamma Table Packet.........= ...........................................................................= .......................................................... = PAGEREF _Toc72921151 \h <= ![endif]-->43

4.3.5&= nbsp;      Frame Buffer Control Pac= ket.........= ...........................................................................= ........................................... 44

4.3.6&= nbsp;      Drawing Packets.........= ...........................................................................= ................................................................. 45

4.3.7&= nbsp;      Transparency Map Packet<= /span>.........= ...........................................................................= ................................................ 50

4.4   &= nbsp;  CRC Algorithm<= span style=3D'mso-tab-count:1 dotted'>..........................................= ...........................................................................= .................................... 51

4.4.1&= nbsp;      Header CRC.........= ...........................................................................= ......................................................................... <= /span>51

4.4.2&= nbsp;      Body CRC.........= ...........................................................................= ...........................................................................= .. 52

5.    Data Format for Monitor Control and Capability M= anagement................................... 54

5.1   &= nbsp;  EDID.................................................................= ...........................................................................= ....................................... 54

5.2   &= nbsp;  DPVL-EXT..........................................= ...........................................................................= ................................................... 54

5.2.1&= nbsp;      Introduction.........= ...........................................................................= ......................................................................... <= /span>54

5.2.2&= nbsp;      DPVL-EXT Format.........= ...........................................................................= .............................................................. 55

5.3   &= nbsp;  MCCS (Monitor Command C= ontrol Set) for DPVL.......................= ...................................................... 68

6.    Conformance Levels..................................................................= ...........................................................................= 70

6.1   &= nbsp;  Monitor Conformance Lev= els..........................................= ...........................................................................= . 70

6.2   &= nbsp;  Host Conformance Levels= ..........................................= ...........................................................................= .......... 71

6.3   &= nbsp;  Host/Monitor Interopera= bility..........................................= ....................................................................... 71

6.4   &= nbsp;  MCCS VCP Requirements f= or Conformance Levels..................= ...................................................... 72

Appendix A =     : FAQ about DPVL....................................................................= ............................................................. 73

Appendix B =     : Example Monitor Report Descriptions..........................................= ............................. 75

Appendix C =     : Example of Header CRC calculation..........................................= .................................. 79

Appendix D =     : Example of Body CRC calculation..........................................= ........................................ 81

Appendix E =     : Delay Estimation Examples.................................................................= ................................. 82

Appendix F =     : Example DPVL-EXT Block.................................................................= ......................................... 84

 

List of Figures

Figure ‎3‑1: System Block Diagram in DPVL.........= ...........................................................................= ........................................ 11

Figure ‎3‑2:= A Generic Frame Structur= e in DPVL...................................................................= ................................................... 12

Figure ‎3‑3:= Diagram of a monitor not capable (top) and capable (bottom) of storing..........................................= .......... 15

Figure ‎3‑4:= Two Aspects of Video Timings in a Monitor with Frame Buffer.................................................................= .... 16

Figure ‎3‑5:= An Example of a Multi-Monitor Configuration in DPVL.................................................................= ................. 19

Figure ‎3‑6:= DPVL HUB Example.........................= ...........................................................................= ........................................... 20

Figure ‎3‑7:= Virtual Screen for Multi-monitor Configurations........................................................................= ........................ 21

Figure ‎3‑8:= Diagram of a monitor not capable of storing whole image when it enters into “Active Off” state AND capable of Link Shutdown (LSD). It shoul= d be interpreted as an overlay to the Figure ‎2-3................................................................ = 23

Figure ‎3‑9:= Image buffer scenarios inside DPVL monitor= ...........................................................................= ........................... 25

Figure ‎3‑10= : Pixel clock counter during one frame time.= ...........................................................................= ............................. 26

Figure ‎4‑1:= Pixel Format for Header Bits..............= ...........................................................................= ......................................... 29

Figure ‎4‑2: Conventions for the Header Format Definition...................................................................= ............................... 30

Figure ‎4‑3:= Basic Header Layout.......................= ...........................................................................= ............................................. 30

Figure ‎4‑4:= Video Packet and Update Rectangle.........= ...........................................................................= ................................. 32

Figure ‎4‑5: Extended Packet Layout..............= ...........................................................................= ................................................ 33

Figure ‎4‑6:= Gamma Table within the DPVL monitor.......= ...........................................................................= ............................ 44

Figure ‎4‑7:= BitBlt Operation in the DPVL Monitor.......= ...........................................................................= ................................ 46

Figure ‎4‑8: Header CRC Timing Diagram.........= ...........................................................................= ....................................... 52

Figure ‎5‑1:= Example of Ultra-Short Vertical Blanking Interval......................................................................= ...................... 61

 =

List of Tables

Table ‎3‑1: Periodic Refresh Requirement..........................................= ...........................................................................= ............ 18

Table ‎3-2: Delay = Table..........................................= ...........................................................................= ............................................ 28

Table ‎4-1: Basic = Header Format..............................= ...........................................................................= ....................................... 31

Table ‎4‑2: = Generic Format for Extended Packets.........= ...........................................................................= ............................... 33

Table ‎4‑3: = Extended Packets described in 4.3.1 through 4.3.5.......................................................................= ...................... 34

Table ‎4‑4: = Field definitions for Extended Packets description fields.................................................................= .................. 39

Table ‎4‑5: = Function number assignment and delay parameter availability for each packet......................................... = 40

Table ‎4‑6: = Video Packet Header Definition............= ...........................................................................= ...................................... 40

Table ‎4‑7: = Genlock Packet Definition...................= ...........................................................................= ......................................... 42

Table ‎4‑8: = Scaled Video Stream Setup Packet Definition= ...........................................................................= .......................... 43

Table ‎4‑9: = Scaled Video Stream Packet Header Definition..........................................................................= ........................ 43

Table ‎4‑10:= Gamma Table Packet Header Definition......= ...........................................................................= .......................... 44

Table ‎4‑11:= Frame Buffer Control Packet Definition....= ...........................................................................= .............................. 45

Table ‎4‑12:= Drawing Packets described in Section 4.3.6.1 through 4.3.6.3.................................................................= ....... 45

Table ‎4‑13:= BitBLT Packet Definition...................= ...........................................................................= ........................................ 47

Table ‎4‑14:= Area Fill Packet Definition..............= ...........................................................................= ............................................ 48

Table ‎4‑15:= Pattern Fill Packet Header Definition.......= ...........................................................................= ................................ 49

Table ‎4‑16: Transparency Map Packet Definition..= ...........................................................................= .................................... 50

= Table ‎5‑1: DPVL-EXT Version 1 Overview..........................................= ...........................................................................= ......... 56

Table ‎5‑2: Data Format Conventions.................................................................= ...................................................................... 56

Table ‎5‑3: Contents of the “General Information” Section..........................................= ........................................................ 57

Table ‎5‑4: = DPVL Standard Version Information........= ...........................................................................= ................................. 58

Table ‎5‑5: Conformance Level Information.......= ...........................................................................= ......................................... 58

Table ‎5‑6: = Contents of the “Display Module Native Timing Information” Section..........................................= ............... 59

Table ‎5‑7: = Contents of the “Transmission Timing” Section.................................................................= ................................. 60

Table ‎5‑8: = Frame Buffer Information..................= ...........................................................................= .......................................... 62

Table ‎5‑9: = Level 2 Supported Extended Packets Information = PAGEREF _Toc72921220 \h <= ![endif]-->63

Table ‎5‑10:= Scaled Video Stream Window Information.....= ...........................................................................= ....................... 64

Table ‎5‑11:= Gamma Table Information...................= ...........................................................................= ..................................... 65

Table ‎5‑12: Contents of the “DPVL Capability Information” Section..........................................= ..................................... 65

Table ‎5‑13:= Delay Parameter Information...............= ...........................................................................= ..................................... 67

Table ‎5‑14:= Checksum..........................................= ...........................................................................= ............................................ 67

Table ‎5‑15:= Monitor Control Command Set for DPVL .......= ...........................................................................= ...................... 68

Table ‎6‑1: = Monitor Conformance Levels..................= ...........................................................................= .................................... 70

Table ‎6‑2: = Host Conformance Levels..................= ...........................................................................= .......................................... 71

Table ‎6‑3: Monitor/Host Interoperability.......= ...........................................................................= ............................................... 72

Table ‎6‑4: = MCCS VCP requirements depending on conformance level....................................................................= ......... 72

 =


1.           &= nbsp;    Preface

1.1           =   Defi= nitions and Conventions

The requirements and specifications for the VESA DPVL standard adhe= re to the following definitions and conventions:

a.)&= nbsp;   Features or functions that are required to be implemented are identified by the word shall in bold type. Failure to adhere to a feature or function identified by s= hall may cause application restrictions, result in improper functioning, or hind= er operations. For a device to be DPVL-compliant, it must implement all featur= es or functions identified by shall.

b.)&= nbsp;   Features or functions that are desirable, but that are not required to be implemented a= re identified by the word should in bold type. Failure to adhere to a feature or function identified by should may inhibit the implementat= ion of some features or functions in specific applications and environments.

c.)&= nbsp;   Features or functions that are optional and are not needed to be implemented are identi= fied by the word may in bold type. Such features or functions represent g= oals to be achieved, and may enhance convenience and utility of VESA DPVL.<= /o:p>

d.)&= nbsp;   Features or= functions that are mentioned by the word “recommended” are strongly considered to become a requirement in future versions of DPVL.

e.)&= nbsp;   The letters= TBD represent the words “to be determined” and indicate that further requirements or specifications are expected to be included in future issues= of this standard.

f.)&= nbsp;    The letter ‘h’ after a number indicates a hexadecimal format and the letter ‘b’ after a number indicates a binary format. If there is no le= tter after a number it means that the number is decimal.

 

1.2      =      Glossary

Basic Packet    = ;            = DPVL frame containing an Basic header and a body section
CRC      &nbs= p;            &= nbsp;         Cyclic Redundancy Check
CRTC      &nb= sp;            =        Cathode Ray Tube Controller
DDC      &nbs= p;            &= nbsp;        Display Data Channel
DDWG      &nb= sp;            =              =      Digital Display Working Group which defined the DVI standard
Display Module           Display device with X and Y drivers plus controller
DE       = ;            &n= bsp;           Data Enable signal on the DVI receiver and transmitter chips
DPVL      &nb= sp;            =        Digital Packet Video Link
DPVL-EXT      = ;            = DPVL Extension Block
DPVL Frame     &nb= sp;          DPVL header plus body
DVI      &nbs= p;            &= nbsp;         Digital Visual Interface Standard as defined by DDWG
E-DDC      &n= bsp;              =      Enhanced Display Data Channel[1] EDID      &nb= sp;            =         Extended Display Identification Data1
E-EDID            =           Enhanced Extended Display Identification Data1
Extended Packet          DPVL frame containing an Extended header and optionally a body section

Frame     =             &nb= sp;        Two dimensional array of video data encapsulated by blanking intervals
GVIF      &nbs= p;            &= nbsp;        Gigabit Video Interface
HPD      &nbs= p;            &= nbsp;         Hot Plug Detect
Integer Expansion    &n= bsp;   Expansion ratios 2:1, 3:1, 4:1, etc.
Integer Shrinkage    &n= bsp;    Shrinkage ratios 1:2, 1:3, 1:4, etc.
LVDS      &nb= sp;            =        Low-Voltage Differential Signaling
MCCS      &nb= sp;            =        Monitor Control Command Set1
Monitor      =             &nb= sp;     Generically used throughout this document to mean a visual display
             =             &nb= sp;          attached to a computer system: examples include a notebook display,
             =             &nb= sp;          desktop monitor, projector, head mounted display, etc.
TMDSTM  &nbs= p;            &= nbsp;      Transition Minimized Differential Signaling
USB      &nbs= p;            &= nbsp;         Universal Serial Bus
Variable Expansion     = Any rational number expansion/shrinkage ratio as long as both the source 
or Shrinkage     &= nbsp;          and destination are an integer number of pixels
Video Frame     &n= bsp;          Generic term for either a raster scan video frame or a DPVL frame   


2.           &= nbsp;    Overview

2.1           =   Summ= ary

This document is the Digital Packet Video Link (DPVL) Standard and defines a high-level video stream protocol enabling high-resolution monitors and cascaded multiple monitors. Such monitors require a higher communication bandwidth than conventional monitor interfaces can provide.

2.2           =   Back= ground

Due to recent advances in display device technologies, monitors are= now capable of providing much higher information content – at higher pixel-density and at higher number of pixels. Such high information content monitors can improve productivity for conventional PC applications. It can = be expected that high pixel-density (e.g. 200 dots per inch) monitors will gain wide popular use. Employing multiple monitors can also provide high informa= tion content, and such systems are becoming increasingly popular in office environments due to the increased productivity they afford.

One of the issues that limit the wide use of high information conte= nt monitors is the conventional monitor interface, which is not adequate for h= igh information content monitors. Though currently digital video interfaces su= ch as TMDS, LVDS and GVIF are becoming popular, they are all based on raster-scan refresh. That is, the host system is required to refresh each p= ixel on the screen many times per second. Thus, high information content monitors require large transmission bandwidth, and the lack of adequate bandwidth on current interfaces limits the monitors update rate.  Raster scan interfaces also lack a mechanism for sending meta data (e.g. various attributes of the video data), which are desirable for flexibility in the video interface.  In addition, this protocol can also be used in bandwidth and/or power constrained systems such as mobile and wireless devices.

2.3           =   Obje= ctives of DPVL

1) The main objective of this standard is to define a selective upd= ate scheme, which allows the host to transmit only modified regions of the scre= en image, and hence decouples the video transmission rate from the refresh rat= e of the display device. This selective update scheme requires the host to embed meta data in the video stream. The monitor uses this meta data to reconstru= ct the entire image of the screen. The DPVL Standard defines video packet structures including meta data formats which permit significant functional extensions.

2) The DPVL Standard also defines a capability management and monit= or control scheme. The capability management scheme allows for the negotiation= of various protocol parameters between the host and monitor. The monitor contr= ol scheme defines a set of monitor control commands that enhances the video st= ream protocol.

3.) Physical-layer protoc= ols, such as electrical signaling protocols and mechanical interfaces, are beyond the scope of this document and are thus not defined herein. DVI has been ch= osen as the physical layer for DPVL within this document. Implementers should re= fer to DVI Revision 1.0 specification. However, it can be envisioned that the D= PVL protocol may be applied to other physical layers.

= 2.4      =        Reference Documents

 

·           Digital Dis= play Working Group (DDWG) – Digital Visual Interface (DVI) Specifications, Revision 1.0, Apr= il 2, 1999

·           USB – Uni= versal Serial Bus Monitor Control Class Specification Revision 1.0 January 5, 1998<= /span>

·           USB – Universal Serial Bus Specification, Revision 1.1, September 23, 1998

·           USB – Universal Serial Bus Specification, Revision 2.0, April 27, 2000

·           VESA – Enhanced Display Data Channel (E-DDCTM) Standard, Version 1, September 2, 1999

·           VESA – Enhanced Extended Display Identification Data (E-EDIDTM) Standar= d, Release A, Rev. 1, February 9, 2000

·      =      VESA – Monitor Control Command Set (MCCSTM) Standard, Version 2.0, October 17, 2003

 


[1] VESA standard

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